The present invention relates to a semiconductor device and a technique for manufacturing the same. Particularly, the present invention is concerned with a surface mount type semiconductor device having testing lands on a lower surface of a wiring substrate with a semiconductor chip mounted thereon, as well as a technique applicable effectively to the manufacture of the semiconductor device.
Semiconductor devices having a surface mount package form such as SiP (System in Package) and BGA (Ball Grid Array) have a structure in which one or plural semiconductor chips (hereinafter referred to merely as the chip) mounted on an upper surface of a wiring substrate called a package substrate are sealed with resin.
Plural wiring lines are formed on an upper surface of the wiring substrate and one ends thereof (bonding leads) and the chip are coupled together electrically through metallic wires or bump electrodes. On the other hand, on a lower surface of the wiring substrate are formed plural lands which are coupled electrically to the above wiring lines through via holes formed within the wiring substrate. These lands configure external terminals of the semiconductor device. The semiconductor device is mounted on a mother board (a package substrate) of any of various electronic devices through solder bumps coupled to these lands.
In addition to the above lands serving as external terminals, testing lands are also provided on the lower surface of the wiring substrate for a semiconductor manufacturer to conduct electrical characteristic tests. In the electrical characteristic tests, metallic contact pins called probes are respectively contacted with the surfaces of the solder bumps and testing lands to determine whether an integrated circuit formed on the chip is good or not or determine whether wiring paths from the chip to lands on the wiring substrate are in conduction or not.
For example, in Patent Document 1 (Japanese Unexamined Patent Publication No. 2006-93189), in connection with an SiP type semiconductor device in which a microcomputer chip and a memory chip are stacked in two stages on an upper surface of a wiring substrate and are sealed with molding resin, there is disclosed a technique of disposing plural electrodes (5c) as external terminals at a peripheral portion of a lower surface of the wiring substrate and further disposing inside the electrodes 5c a plurality of electrodes (5d) as testing terminals to conduct evaluation, reliability test and defect analysis of the memory chip.
Solder bumps are coupled to the electrodes 5c serving as external terminals of the above SiP, while solder bumps are not coupled to the electrodes 5d serving as testing terminals, affording a flat LGA (Land Grid Array). The pitch of adjacent electrodes 5d is the same as that of adjacent electrodes 5c, but the electrodes 5d are smaller in diameter than the electrodes 5c. Further, the surfaces of the electrodes 5d are covered with solder resist to decrease the potential of short-circuit with the solder bumps coupled to the electrodes 5c. For testing the memory chip, the solder resist which covers the surface of each electrode 5d is removed and a probe is contacted with the exposed electrode 5d. 
In Patent Document 2 (Japanese Unexamined Patent Publication No. 2009-49170), in connection with a semiconductor device having a surface mount package form like SiP or BGA, there is disclosed a technique in which bumps coupled to external terminals are sorted into those large in diameter and pitch and those small in diameter and pitch and the latter bumps are disposed close to the center of a wiring substrate rather than the former bumps.
A portion of the above large bumps are used for coupling between the semiconductor device and the package substrate, while another portion of the large bumps are not used for coupling with the package substrate but are used for coupling to a screening tester. On the other hand, the small bumps are used neither for coupling to the package substrate nor for coupling to the screening tester. The small bumps are testing bumps which the semiconductor manufacturer uses to test electrical characteristics before shipping.
According to the above configuration, even if a wiring pattern is disposed on the package substrate at a position just under the area of small bumps when the semiconductor device is mounted onto the package substrate through the large bumps, an undesired short-circuit between the wiring pattern and the associated testing bump is avoided. As a result, it is not required to provide a wiring pattern-free area on the package substrate and hence the package-side restriction for suppressing the undesired short-circuit with the testing bump is moderated.